Embedded {hardware} specialist Renesas has introduced its first absolutely in-house processor core based mostly on the free and open RISC-V instruction set structure (ISA) — marking a transfer away from utilizing third-party core designs, together with these from business big Arm.
“The growing reputation of the RISC-V ISA inside the semiconductor business is a boon for innovation. It gives designers with unprecedented flexibility and can slowly however steadily problem and remodel the present panorama of embedded techniques,” Renesas’ Giancarlo Parodi says of the know-how behind the corporate’s newest microcontroller. “Prior to now, Renesas has embraced RISC-V know-how introducing 32-bit ASSP units for voice-control and motor-control constructed on CPU cores developed by Andes Expertise Corp. The thrilling subsequent step is the supply of [our] first in-house engineered CPU core.”
Renesas is making the soar into CPU IP design, asserting its first in-house RISC-V core design — hitting the market early 2024. (📷: Renesas)
Whereas Renesas is not sharing full product particulars on the elements which is able to use its in-house core but, it has confirmed a number of technical particulars concerning the core itself. A block diagram reveals a single 32-bit RISC-V core with performance-boosting dynamic department predictor, a {hardware} multiplier/divider, a vectored interrupt controller, a stack monitor register, separate instruction and information buses ,and compact JTAG (cJTAG)/JTAG debug capabilities. It has additionally promised a 3.27 CoreMark per megahertz (CoreMark/MHz) efficiency degree — although at an as-yet unknown clock velocity.
“This CPU is appropriate for a lot of totally different software contexts. It may be used as most important CPU or to handle an on-chip subsystem and even to be embedded in a specialised ASSP [Application-Specific Standard Product] gadget,” Parodi claims. “Clearly it is rather versatile. Second, the implementation could be very environment friendly when it comes to silicon space, which helps cut back working present and leakage present throughout standby time, moreover the apparent impact of smaller price impression. Third, regardless of focusing on small embedded techniques, it gives a surprisingly excessive degree of computational throughput to meet the more and more demanding efficiency requirement of even deeply embedded functions.”
Renesas has already launched elements with RISC-V cores, however solely utilizing third-party IP from Andes Expertise. (📷: Renesas)
The core makes use of the free and open RISC-V instruction set structure, together with a number of of its extensions: Parodi says the core implements the RV32I or RV32E ISA with multiplication (M), atomic entry (A), compressed directions (C), and bit-manipulation (B) extensions. “That is the great thing about the RISC-V ISA idea,” Parodi claims, “constructed from the ground-up to permit the designer to decide on which components to incorporate within the processor, depending on their goal use case, and because of this optimize the trade-off between the ensuing energy consumption, efficiency, and silicon footprint.”
Renesas says it’s sampling silicon with the brand new core to “choose clients” now, with the primary business chips attributable to launch within the first quarter of subsequent 12 months. Extra data is on the market in Parodi’s weblog put up.